A Standardized Procedure for the Direct Measurement of Sub-Picosecond RMS jitter in High-Speed Analog-to-Digital Converters

The advent of modern-day wireless communications systems as well as other high speed applications imposes exceedingly challenging demands on state-of-the-art Analog-to-Digital Converters (ADCs). The evolution of receiver architectures necessitates very high Signal-to-Noise Ratio (SNR) at intermediate frequencies that up until recently were impossible to achieve. Recent breakthroughs in converter architectures and silicon processes have however enabled the attainment of the required signal purity at input frequencies in excess of 100MHz. The predominant mechanism limiting high SNR at very high input frequencies in sampled systems is the timing (aperture) uncertainty of the sampling instant, commonly referred to as jitter. In order to achieve the required performance, today's best ADCs must feature jitter significantly below 1ps RMS. The ADS5420, a 14-bit 65MSps ADC from Texas Instruments, is specifically designed for high-IF sampling application and features industry-leading levels of jitter. This application note proposes an innovative, reliable characterization technique that allows to measure ultra-low jitter levels while also discriminating noise contributions due to jitter from other phenomena (voltage reference and substrate noise, high-amplitude distortion) in ADCs. The jitter estimated with this method closely matches the one inferred from the SNR at high input frequencies, where noise is dominated by the aperture uncertainty. The document outlines therefore a standardized way for measuring and specifying jitter in ADCs, i.e. it proposes the unified test procedure that is notoriously absent in industry today. Moreover, at the sub-picosecond resolution level required by the 14-bit high-IF ADC under test, any off-chip disturbances substantially affect the accuracy of the measurement also. In order to characterize the uncertainty, we show how the phase noise spectrum of the external clock source can be measured and converted into jitter by way of a rigorous formula. INTRODUCTION As the demand for high fidelity sampling of input frequencies in excess of 10MHz continues to increase, the aperture uncertainty (jitter) of the ADC itself is becoming the limiting factor of the achievable SNR of the whole signal-conditioning chain. Numerous methodologies have been proposed and discussed, since jitter performance still is one of the most challenging issues in state-of-the-art sampled systems [1-3]. The simplest and most widely adopted one infers the jitter value from the SNR measurements at high input frequency, where the random deviation σT of the occurrence of the sampling edge translates into a random voltage error σVjitter that dominates the noise deviation σV. The retro-fitting is usually accomplished according to the formula [4]: